Complementary Metal-Oxide-Semiconductor (CMOS) devices are being scaled down aggressively in each technology generation to achieve higher integration density. However, the scaling of CMOS devices is approaching its physical limitations. For example, one significant factor limiting MOS scaling is off-state power consumption. Within digital logic, the sources that contribute to off-state power consumption include junction leakage, gate induced drain leakage, subthreshold channel current, and gate tunnel currents. These become increasingly significant as the dimensions decrease. For instance, when the length of the channel (the channel can be visualized as the “stream” through which charges (e.g., electrons, holes) flow from the source to the drain of the transistor) in the CMOS device becomes so short, such as on the order of 20 nm, the transistor is unable to be turned off because of undesirable leakage current between the source and the drain. As a result, new materials and device structures are needed to enable further performance improvements.